ProbLock: Probability-based Logic Locking
This addresses hardware security threats for circuit designers, but appears incremental as it builds on existing logic locking methods.
The paper tackles the problem of integrated circuit piracy and overproduction by developing a probability-based logic locking technique called ProbLock, which selects key gate locations based on constraints and was tested on 40 benchmarks from ISCAS suites.
Integrated circuit (IC) piracy and overproduction are serious issues that threaten the security and integrity of a system. Logic locking is a type of hardware obfuscation technique where additional key gates are inserted into the circuit. Only the correct key can unlock the functionality of that circuit otherwise the system produces the wrong output. In an effort to hinder these threats on ICs, we have developed a probability-based logic locking technique to protect the design of a circuit. Our proposed technique called "ProbLock" can be applied to combinational and sequential circuits through a critical selection process. We used a filtering process to select the best location of key gates based on various constraints. Each step in the filtering process generates a subset of nodes for each constraint. We also analyzed the correlation between each constraint and adjusted the strength of the constraints before inserting key gates. We have tested our algorithm on 40 benchmarks from the ISCAS '85 and ISCAS '89 suite.