Model Synthesis for Communication Traces of System-on-Chip Designs
This provides a method for generating abstract models to aid in design analysis and validation for system-on-chip engineers, but it appears incremental as it applies existing SMT solving techniques to this domain.
The paper tackles the problem of inferring models from communication traces of system-on-chip designs by formulating it as a constraint satisfaction problem solved with an SMT solver, and demonstrates the approach on traces from transaction-level and GEM5 simulation models.
Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of inferring models from communication traces of system-on-chip~(SoC) designs. The traces capture communications among different blocks of a SoC design in terms of messages exchanged. The extracted models characterize the system-level communication protocols governing how blocks exchange messages, and coordinate with each other to realize various system functions. In this paper, the above problem is formulated as a constraint satisfaction problem, which is then fed to a SMT solver. The solutions returned by the SMT solver are used to extract the models that accept the input traces. In the experiments, we demonstrate the proposed approach with traces collected from a transaction-level simulation model of a multicore SoC design and traces of a more detailed multicore SoC design developed in GEM5 environment.