Quantifying the Efficacy of Logic Locking Methods
This work addresses the critical impediment for designers in choosing effective logic locking methods to secure outsourced manufacturing, though it appears incremental as it focuses on evaluation metrics rather than new protection methods.
The paper tackled the problem of evaluating logic locking methods for protecting integrated circuits from intellectual property theft by proposing two metrics, key corruption and minimum corruption, to assess their efficacy under different attack scenarios, and evaluated several techniques using a developed flow.
The outsourced manufacturing of integrated circuits has increased the risk of intellectual property theft. In response, logic locking techniques have been developed for protecting designs by adding programmable elements to the circuit. These techniques differ significantly in both overhead and resistance to various attacks, leaving designers unable to discern their efficacy. To overcome this critical impediment for the adoption of logic locking, we propose two metrics, key corruption and minimum corruption, that capture the goals of locking under different attack scenarios. We develop a flow for approximating these metrics on generic locked circuits and evaluate several locking techniques.