A matrix math facility for Power ISA(TM) processors
This work provides a power- and area-efficient hardware solution for accelerating linear algebra operations in Power ISA processors, which is incremental as it builds on existing processor generations.
The paper introduces the Matrix-Multiply Assist (MMA) facility in Power ISA Version 3.1 to accelerate computation-intensive kernels like matrix multiplication and convolution, resulting in a 4x performance improvement per core in the POWER10 processor compared to POWER9.
Power ISA(TM) Version 3.1 has introduced a new family of matrix math instructions, collectively known as the Matrix-Multiply Assist (MMA) facility. The instructions in this facility implement numerical linear algebra operations on small matrices and are meant to accelerate computation-intensive kernels, such as matrix multiplication, convolution and discrete Fourier transform. These instructions have led to a power- and area-efficient implementation of a high throughput math engine in the future POWER10 processor. Performance per core is 4 times better, at constant frequency, than the previous generation POWER9 processor. We also advocate the use of compiler built-ins as the preferred way of leveraging these instructions, which we illustrate through case studies covering matrix multiplication and convolution.