A Connected Component Labelling algorithm for multi-pixel per clock cycle video stream
This work addresses the need for efficient video processing in hardware for applications like computer vision, though it is incremental as it builds on existing CCL methods with optimizations for specific formats.
The authors tackled the problem of real-time connected component labeling for high-resolution video streams by developing a hardware module that fully supports 4 pixels per clock processing, achieving real-time performance for 4K video at 60 fps.
This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the "full", i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.