An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes
This work addresses the problem of deploying iris recognition on embedded systems for nation-scale applications, but it is incremental as it builds on existing QC-LDPC codes and dynamic reconfiguration techniques.
The paper tackles the high complexity of iris recognition systems for embedded devices by proposing a design with minimal computer vision modules and a multi-mode QC-LDPC decoder to reduce noise, showing that the implementation is power-efficient and suitable for edge applications.
Extracting and analyzing iris textures for biometric recognition has been extensively studied. As the transition of iris recognition from lab technology to nation-scale applications, most systems are facing high complexity in either time or space, leading to unfitness for embedded devices. In this paper, the proposed design includes a minimal set of computer vision modules and multi-mode QC-LDPC decoder which can alleviate variability and noise caused by iris acquisition and follow-up process. Several classes of QC-LDPC code from IEEE 802.16 are tested for the validity of accuracy improvement. Some of the codes mentioned above are used for further QC-LDPC decoder quantization, validation and comparison to each other. We show that we can apply Dynamic Partial Reconfiguration technology to implement the multi-mode QC-LDPC decoder for the iris recognition system. The results show that the implementation is power-efficient and good for edge applications.