NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
This addresses the problem of efficient chip design automation for the semiconductor industry, representing a strong specific gain.
The paper tackled the challenge of automating high-quality standard cell layout in advanced technology nodes with complex design rules by introducing NVCell, an automatic generator that produced layouts with equal or smaller area for over 90% of single row cells in an industry library.
High quality standard cell layout automation in advanced technology nodes is still challenging in the industry today because of complex design rules. In this paper we introduce an automatic standard cell layout generator called NVCell that can generate layouts with equal or smaller area for over 90% of single row cells in an industry standard cell library on an advanced technology node. NVCell leverages reinforcement learning (RL) to fix design rule violations during routing and to generate efficient placements.