VeRLPy: Python Library for Verification of Digital Designs with Reinforcement Learning
This work addresses verification delays in electronic design automation by providing a tool that reduces engineering overhead, though it is incremental as it builds on existing RL approaches.
The paper tackles the problem of inefficient random input generation in digital hardware verification by introducing VeRLPy, an open-source Python library that uses reinforcement learning to prioritize inputs for better design exploration, demonstrating its value over random methods.
Digital hardware is verified by comparing its behavior against a reference model on a range of randomly generated input signals. The random generation of the inputs hopes to achieve sufficient coverage of the different parts of the design. However, such coverage is often difficult to achieve, amounting to large verification efforts and delays. An alternative is to use Reinforcement Learning (RL) to generate the inputs by learning to prioritize those inputs which can more efficiently explore the design under test. In this work, we present VeRLPy an open-source library to allow RL-driven verification with limited additional engineering overhead. This contributes to two broad movements within the EDA community of (a) moving to open-source toolchains and (b) reducing barriers for development with Python support. We also demonstrate the use of VeRLPy for a few designs and establish its value over randomly generated input signals.