Guiding Global Placement With Reinforcement Learning
This work addresses chip design optimization for the semiconductor industry, representing an incremental improvement over existing methods.
The paper tackled the problem of improving placement quality in chip design by augmenting force-based global placement solvers with reinforcement learning agents, achieving an average 1% improvement in final detail place Half Perimeter Wire Length (HPWL) on academic benchmarks and over 1% in global place HPWL on real industry designs.
Recent advances in GPU accelerated global and detail placement have reduced the time to solution by an order of magnitude. This advancement allows us to leverage data driven optimization (such as Reinforcement Learning) in an effort to improve the final quality of placement results. In this work we augment state-of-the-art, force-based global placement solvers with a reinforcement learning agent trained to improve the final detail placed Half Perimeter Wire Length (HPWL). We propose novel control schemes with either global or localized control of the placement process. We then train reinforcement learning agents to use these controls to guide placement to improved solutions. In both cases, the augmented optimizer finds improved placement solutions. Our trained agents achieve an average 1% improvement in final detail place HPWL across a range of academic benchmarks and more than 1% in global place HPWL on real industry designs.