Self-Learning Tuning for Post-Silicon Validation
This addresses the challenge of design validation for chip manufacturers, but appears incremental as it builds on existing learn-to-optimize and reinforcement learning methods.
The paper tackles the problem of robust performance tuning in post-silicon validation for modern chips, proposing a novel approach based on learn-to-optimize and reinforcement learning to solve complex and mixed-type tuning tasks efficiently and robustly.
Increasing complexity of modern chips makes design validation more difficult. Existing approaches are not able anymore to cope with the complexity of tasks such as robust performance tuning in post-silicon validation. Therefore, we propose a novel approach based on learn-to-optimize and reinforcement learning in order to solve complex and mixed-type tuning tasks in a efficient and robust way.