Testability-Aware Low Power Controller Design with Evolutionary Learning
This addresses incremental improvements in low power controller design for circuit testing, benefiting engineers in reducing test data volume and time.
The paper tackles the problem of sub-optimal XORNet-based low power controllers in scan-based testing by proposing a testability-aware design with evolutionary learning, resulting in up to 2.11% higher fault coverage and average 20.78% reduction in testing time.
XORNet-based low power controller is a popular technique to reduce circuit transitions in scan-based testing. However, existing solutions construct the XORNet evenly for scan chain control, and it may result in sub-optimal solutions without any design guidance. In this paper, we propose a novel testability-aware low power controller with evolutionary learning. The XORNet generated from the proposed genetic algorithm (GA) enables adaptive control for scan chains according to their usages, thereby significantly improving XORNet encoding capacity, reducing the number of failure cases with ATPG and decreasing test data volume. Experimental results indicate that under the same control bits, our GA-guided XORNet design can improve the fault coverage by up to 2.11%. The proposed GA-guided XORNets also allows reducing the number of control bits, and the total testing time decreases by 20.78% on average and up to 47.09% compared to the existing design without sacrificing test coverage.