IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption
This work addresses the need for efficient hardware acceleration of cryptographic operations, particularly for applications requiring high-speed and low-power AES processing, though it appears incremental as it builds on existing in-memory computing concepts.
The paper tackles the problem of accelerating AES encryption and decryption by proposing IMCRYPTO, an in-memory computing fabric that achieves high throughput without sacrificing area and power, with improvements in throughput per area ranging from 3.3x to 223.1x compared to previous architectures.
This paper proposes IMCRYPTO, an in-memory computing (IMC) fabric for accelerating AES encryption and decryption. IMCRYPTO employs a unified structure to implement encryption and decryption in a single hardware architecture, with combined (Inv)SubBytes and (Inv)MixColumns steps. Because of this step-combination, as well as the high parallelism achieved by multiple units of random-access memory (RAM) and random-access/content-addressable memory (RA/CAM) arrays, IMCRYPTO achieves high throughput encryption and decryption without sacrificing area and power consumption. Additionally, due to the integration of a RISC-V core, IMCRYPTO offers programmability and flexibility. IMCRYPTO improves the throughput per area by a minimum (maximum) of 3.3x (223.1x) when compared to previous ASICs/IMC architectures for AES-128 encryption. Projections show added benefit from emerging technologies of up to 5.3x to the area-delay-power product of IMCRYPTO.