A Survey of Deep Learning Techniques for Dynamic Branch Prediction
It addresses the problem of improving processor efficiency for computer architecture researchers, but is incremental as it builds on prior surveys with updated DL research.
This survey paper examines the application of deep learning techniques to dynamic branch prediction, analyzing traditional algorithms and their limitations to explore how DL can enhance predictors for conditional branch instructions.
Branch prediction is an architectural feature that speeds up the execution of branch instruction on pipeline processors and reduces the cost of branching. Recent advancements of Deep Learning (DL) in the post Moore's Law era is accelerating areas of automated chip design, low-power computer architectures, and much more. Traditional computer architecture design and algorithms could benefit from dynamic predictors based on deep learning algorithms which learns from experience by optimizing its parameters on large number of data. In this survey paper, we focus on traditional branch prediction algorithms, analyzes its limitations, and presents a literature survey of how deep learning techniques can be applied to create dynamic branch predictors capable of predicting conditional branch instructions. Prior surveys in this field focus on dynamic branch prediction techniques based on neural network perceptrons. We plan to improve the survey based on latest research in DL and advanced Machine Learning (ML) based branch predictors.