Horizontal Attacks against ECC: from Simulations to ASIC
This work addresses side-channel vulnerability in hardware security for ECC, providing incremental insights into compile option impacts on ASIC resistance.
The paper analyzes how different compile options affect the success rate of side-channel attacks on ECC implementations, finding that the compile_ultra option reduces the success rate from 5 key candidates (75-90% correctness) to 3 candidates (max 72% success).
In this paper we analyse the impact of different compile options on the success rate of side-channel analysis attacks. We run horizontal differential side-channel attacks against simulated power traces for the same $kP$ design synthesized using two different compile options after synthesis and after layout. As we are interested in the effect on the produced ASIC we also run the same attack against measured power traces after manufacturing the ASIC. We found that the compile_ultra option reduces the success rate significantly from 5 key candidates with a correctness of between 75 and 90 per cent down to 3 key candidates with a maximum success rate of 72 per cent compared to the simple compile option. Also the success rate after layout shows a very high correlation with the one obtained attacking the measured power and electromagnetic traces, i.e. the simulations are a good indicator of the resistance of the ASIC.