TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks
This work addresses security issues in integrated circuit protection for hardware designers, offering a method to enhance resilience against advanced attacks, though it appears incremental as it builds on existing locking techniques.
The authors tackled the vulnerability of sequential logic locking to SAT-based and removal attacks by proposing TriLock, which achieves tunable functional corruptibility and guarantees exponential SAT solver queries while obscuring locking components to resist detection and removal.
Sequential logic locking has been studied over the last decade as a method to protect sequential circuits from reverse engineering. However, most of the existing sequential logic locking techniques are threatened by increasingly more sophisticated SAT-based attacks, efficiently using input queries to a SAT solver to rule out incorrect keys, as well as removal attacks based on structural analysis. In this paper, we propose TriLock, a sequential logic locking method that simultaneously addresses these vulnerabilities. TriLock can achieve high, tunable functional corruptibility while still guaranteeing exponential queries to the SAT solver in a SAT-based attack. Further, it adopts a state re-encoding method to obscure the boundary between the original state registers and those inserted by the locking method, thus making it more difficult to detect and remove the locking-related components.