Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures
This work addresses performance degradation in RRAM accelerators for deep learning, offering insights into mapping schemes, but it is incremental as it builds on existing DSE methods.
The paper presents an extended Design Space Exploration methodology to quantify the benefits and limitations of dense and sparse mapping schemes for RRAM accelerators, finding that sparse schemes are more susceptible to noise in tiled arrays compared to dense ones, with trade-offs formalized using the CIFAR-10 dataset.
The impact of device and circuit-level effects in mixed-signal Resistive Random Access Memory (RRAM) accelerators typically manifest as performance degradation of Deep Learning (DL) algorithms, but the degree of impact varies based on algorithmic features. These include network architecture, capacity, weight distribution, and the type of inter-layer connections. Techniques are continuously emerging to efficiently train sparse neural networks, which may have activation sparsity, quantization, and memristive noise. In this paper, we present an extended Design Space Exploration (DSE) methodology to quantify the benefits and limitations of dense and sparse mapping schemes for a variety of network architectures. While sparsity of connectivity promotes less power consumption and is often optimized for extracting localized features, its performance on tiled RRAM arrays may be more susceptible to noise due to under-parameterization, when compared to dense mapping schemes. Moreover, we present a case study quantifying and formalizing the trade-offs of typical non-idealities introduced into 1-Transistor-1-Resistor (1T1R) tiled memristive architectures and the size of modular crossbar tiles using the CIFAR-10 dataset.