High-level Synthesis using the Julia Language
This addresses the problem of accessibility for users in industrial and research applications by reducing the need for extensive training, though it appears incremental as it builds on existing HLS concepts with a new language implementation.
The paper tackles the high barrier to entry in High-level Synthesis (HLS) tools for FPGA hardware acceleration by proposing a prototype HLS tool based on the Julia language, which transforms Julia code to VHDL to leverage its readability and existing libraries.
The growing proliferation of FPGAs and High-level Synthesis (HLS) tools has led to a large interest in designing hardware accelerators for complex operations and algorithms. However, existing HLS toolflows typically require a significant amount of user knowledge or training to be effective in both industrial and research applications. In this paper, we propose using the Julia language as the basis for an HLS tool. The Julia HLS tool aims to decrease the barrier to entry for hardware acceleration by taking advantage of the readability of the Julia language and by allowing the use of the existing large library of standard mathematical functions written in Julia. We present a prototype Julia HLS tool, written in Julia, that transforms Julia code to VHDL. We highlight how features of Julia and its compiler simplified the creation of this tool, and we discuss potential directions for future work.