Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning
This work addresses the problem of flexible hardware design for ML workloads, offering a solution for both server and edge applications, but it is incremental as it builds on existing analog computing principles.
The paper tackles the challenge of designing machine learning processors that can adapt to different power-performance needs, such as high throughput for servers and energy efficiency for edge devices, by implementing a bias-scalable analog computing core using shape-based analog computing (S-AC) in a 180nm CMOS process, demonstrating robust performance under transistor biasing and temperature variations.
Bias-scalable analog computing is attractive for implementing machine learning (ML) processors with distinct power-performance specifications. For instance, ML implementations for server workloads are focused on higher computational throughput for faster training, whereas ML implementations for edge devices are focused on energy-efficient inference. In this paper, we demonstrate the implementation of bias-scalable approximate analog computing circuits using the generalization of the margin-propagation principle called shape-based analog computing (S-AC). The resulting S-AC core integrates several near-memory compute elements, which include: (a) non-linear activation functions; (b) inner-product compute circuits; and (c) a mixed-signal compressive memory, all of which can be scaled for performance or power while preserving its functionality. Using measured results from prototypes fabricated in a 180nm CMOS process, we demonstrate that the performance of computing modules remains robust to transistor biasing and variations in temperature. In this paper, we also demonstrate the effect of bias-scalability and computational accuracy on a simple ML regression task.