LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
This addresses congestion prediction for VLSI design, offering a domain-specific incremental advance.
The paper tackles the problem of predicting congestion in VLSI circuit placement by proposing a lattice hypergraph formulation and LHNN neural network, achieving over 35% improvement in F1 score compared to U-nets and Pix2Pix.
Precise congestion prediction from a placement solution plays a crucial role in circuit placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation for circuits, which preserves netlist data during the whole learning process, and enables the congestion information propagated geometrically and topologically. Based on the formulation, we further developed a heterogeneous graph neural network architecture LHNN, jointing the routing demand regression to support the congestion spot classification. LHNN constantly achieves more than 35% improvements compared with U-nets and Pix2Pix on the F1 score. We expect our work shall highlight essential procedures using machine learning for congestion prediction.