Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays
This work addresses power and area efficiency for compute-intensive inner products in hardware design, representing an incremental improvement over existing online multipliers.
The paper tackles the problem of high power and area consumption in multipliers for inner product arrays by proposing a pipelined multiplier with truncated working precision and variable digit slices, achieving up to 38% power reduction and 44% area reduction compared to non-truncated pipelined online multipliers.
We present a pipelined multiplier with reduced activities and minimized interconnect based on online digit-serial arithmetic. The working precision has been truncated such that $p<n$ bits are used to compute $n$ bits product, resulting in significant savings in area and power. The digit slices follow variable precision according to input, increasing upto $p$ and then decreases according to the error profile. Pipelining has been done to achieve high throughput and low latency which is desirable for compute intensive inner products. Synthesis results of the proposed designs have been presented and compared with the non-pipelined online multiplier, pipelined online multiplier with full working precision and conventional serial-parallel and array multipliers. For $8, 16, 24$ and $32$ bit precision, the proposed low power pipelined design show upto $38\%$ and $44\%$ reduction in power and area respectively compared to the pipelined online multiplier without working precision truncation.