Sparse Compressed Spiking Neural Network Accelerator for Object Detection
This work addresses the problem of efficient hardware acceleration for SNN-based object detection, offering incremental improvements in energy efficiency and speed for embedded or low-power applications.
The paper tackles the challenge of high buffer requirements and long inference times in spiking neural network (SNN) accelerators for object detection by proposing a sparse compressed accelerator that leverages high sparsity in activations and weights. The result is a system achieving 71.5% mAP on the IVS 3cls dataset, with the accelerator processing 1024x576@29 fps at 500MHz, 35.88 TOPS/W energy efficiency, and 1.05mJ per frame.
Spiking neural networks (SNNs), which are inspired by the human brain, have recently gained popularity due to their relatively simple and low-power hardware for transmitting binary spikes and highly sparse activation maps. However, because SNNs contain extra time dimension information, the SNN accelerator will require more buffers and take longer to infer, especially for the more difficult high-resolution object detection task. As a result, this paper proposes a sparse compressed spiking neural network accelerator that takes advantage of the high sparsity of activation maps and weights by utilizing the proposed gated one-to-all product for low power and highly parallel model execution. The experimental result of the neural network shows 71.5$\%$ mAP with mixed (1,3) time steps on the IVS 3cls dataset. The accelerator with the TSMC 28nm CMOS process can achieve 1024$\times$576@29 frames per second processing when running at 500MHz with 35.88TOPS/W energy efficiency and 1.05mJ energy consumption per frame.