HyperTensioN and Total-order Forward Decomposition optimizations
This work addresses runtime inefficiencies for domain experts using HTN planners, but it is incremental as it builds on existing compiler and optimization techniques.
The paper tackles the problem of inefficient Hierarchical Task Networks (HTN) planning due to redundant or rarely used domain descriptions, and it shows that a three-stage compiler design with preprocessing optimizations can greatly improve runtime efficiency, as evaluated with the HyperTensioN planner in the HTN IPC 2020.
Hierarchical Task Networks (HTN) planners generate plans using a decomposition process with extra domain knowledge to guide search towards a planning task. While domain experts develop HTN descriptions, they may repeatedly describe the same preconditions, or methods that are rarely used or possible to be decomposed. By leveraging a three-stage compiler design we can easily support more language descriptions and preprocessing optimizations that when chained can greatly improve runtime efficiency in such domains. In this paper we evaluate such optimizations with the HyperTensioN HTN planner, used in the HTN IPC 2020.