Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm
This addresses noise reduction in event streams for autonomous vehicle perception systems, representing an incremental improvement with specific hardware optimization.
The paper tackles noise filtering in neuromorphic vision for autonomous vehicles by presenting a novel IIR filter matrix algorithm and a hardware architecture on an SoC FPGA, achieving over 99% noise removal and a throughput of up to 385.8 MEPS.
Neuromorphic vision is a rapidly growing field with numerous applications in the perception systems of autonomous vehicles. Unfortunately, due to the sensors working principle, there is a significant amount of noise in the event stream. In this paper we present a novel algorithm based on an IIR filter matrix for filtering this type of noise and a hardware architecture that allows its acceleration using an SoC FPGA. Our method has a very good filtering efficiency for uncorrelated noise - over 99% of noisy events are removed. It has been tested for several event data sets with added random noise. We designed the hardware architecture in such a way as to reduce the utilisation of the FPGA's internal BRAM resources. This enabled a very low latency and a throughput of up to 385.8 MEPS million events per second.The proposed hardware architecture was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the Mercury+ XU9 module with the Mercury+ ST1 base board.