Mining SoC Message Flows with Attention Model
This addresses the daunting task of validation for SoC designers, but it appears incremental as it builds on existing trace mining tools with a novel method.
The paper tackles the problem of manually developing and maintaining system-level message flow specifications for SoC designs by proposing a method using deep sequence modeling with attention to infer accurate specifications from communication traces, and it outperforms existing state-of-the-art trace mining tools in experiments on five highly concurrent traces.
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of such specifications are daunting tasks. We propose a disruptive method that utilizes deep sequence modeling with the attention mechanism to infer accurate flow specifications from SoC communication traces. The proposed method can overcome the inherent complexity of SoC traces induced by the concurrent executions of SoC designs that existing mining tools often find extremely challenging. We conduct experiments on five highly concurrent traces and find that the proposed approach outperforms several existing state-of-the-art trace mining tools.