GRANITE: A Graph Neural Network Model for Basic Block Throughput Estimation
This addresses the labor-intensive task of developing analytical hardware performance models for modern processors, benefiting compiler optimization and performance analysis, though it is incremental as it builds on existing machine learning approaches for performance estimation.
The paper tackles the problem of estimating basic block throughput across different microarchitectures by introducing GRANITE, a graph neural network model that achieves a new state-of-the-art with an average test error of 6.9%, reducing error by 1.7% and improving training and inference throughput by approximately 3.0x compared to recent work.
Analytical hardware performance models yield swift estimation of desired hardware performance metrics. However, developing these analytical models for modern processors with sophisticated microarchitectures is an extremely laborious task and requires a firm understanding of target microarchitecture's internal structure. In this paper, we introduce GRANITE, a new machine learning model that estimates the throughput of basic blocks across different microarchitectures. GRANITE uses a graph representation of basic blocks that captures both structural and data dependencies between instructions. This representation is processed using a graph neural network that takes advantage of the relational information captured in the graph and learns a rich neural representation of the basic block that allows more precise throughput estimation. Our results establish a new state-of-the-art for basic block performance estimation with an average test error of 6.9% across a wide range of basic blocks and microarchitectures for the x86-64 target. Compared to recent work, this reduced the error by 1.7% while improving training and inference throughput by approximately 3.0x. In addition, we propose the use of multi-task learning with independent multi-layer feed forward decoder networks. Our results show that this technique further improves precision of all learned models while significantly reducing per-microarchitecture training costs. We perform an extensive set of ablation studies and comparisons with prior work, concluding a set of methods to achieve high accuracy for basic block performance estimation.