TPU-MLIR: A Compiler For TPU Using MLIR
This work addresses the challenge of building efficient compilers for domain-specific hardware like TPUs, which is incremental as it leverages existing MLIR infrastructure to reduce development costs.
The authors tackled the problem of deploying pre-trained neural network models to custom Tensor Processing Units (TPUs) by developing TPU-MLIR, an end-to-end compiler based on MLIR that defines new dialects for graph semantics and kernel computation, resulting in a system that optimizes and verifies transformations for efficient machine code generation.
Multi-level intermediate representations (MLIR) show great promise for reducing the cost of building domain-specific compilers by providing a reusable and extensible compiler infrastructure. This work presents TPU-MLIR, an end-to-end compiler based on MLIR that deploys pre-trained neural network (NN) models to a custom ASIC called a Tensor Processing Unit (TPU). TPU-MLIR defines two new dialects to implement its functionality: 1. a Tensor operation (TOP) dialect that encodes the deep learning graph semantics and independent of the deep learning framework and 2. a TPU kernel dialect to provide a standard kernel computation on TPU. A NN model is translated to the TOP dialect and then lowered to the TPU dialect for different TPUs according to the chip's configuration. We demonstrate how to use the MLIR pass pipeline to organize and perform optimization on TPU to generate machine code. The paper also presents a verification procedure to ensure the correctness of each transform stage.