Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs
This is an incremental review and pipeline proposal for using GNNs in IC design, addressing problems for researchers and practitioners in electronics and machine learning.
The paper tackles the challenge of applying graph neural networks (GNNs) to integrated circuit (IC) design by proposing a generic pipeline for tailoring GNN models, and it provides a comprehensive overview covering electronic design automation, reliability, and security, including examples like breaking state-of-the-art logic obfuscation.
Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since integrated circuits (ICs) can naturally be represented as graphs, there has been a tremendous surge in employing GNNs for machine learning (ML)-based methods for various aspects of IC design. Given this trajectory, there is a timely need to review and discuss some powerful and versatile GNN approaches for advancing IC design. In this paper, we propose a generic pipeline for tailoring GNN models toward solving challenging problems for IC design. We outline promising options for each pipeline element, and we discuss selected and promising works, like leveraging GNNs to break SOTA logic obfuscation. Our comprehensive overview of GNNs frameworks covers (i) electronic design automation (EDA) and IC design in general, (ii) design of reliable ICs, and (iii) design as well as analysis of secure ICs. We provide our overview and related resources also in the GNN4IC hub at https://github.com/DfX-NYUAD/GNN4IC. Finally, we discuss interesting open problems for future research.