High-Dimensional Yield Estimation using Shrinkage Deep Features and Maximization of Integral Entropy Reduction
This work addresses efficiency challenges in circuit yield estimation for chip designers, offering a practical incremental improvement over existing methods.
The paper tackles the curse of dimensionality in high-sigma yield analysis for large-scale circuits by proposing ASDK, a method that identifies dominant process variation parameters and uses a surrogate model to emulate expensive SPICE simulations, achieving up to 10.3x speedup over state-of-the-art methods in experiments on SRAM column circuits.
Despite the fast advances in high-sigma yield analysis with the help of machine learning techniques in the past decade, one of the main challenges, the curse of dimensionality, which is inevitable when dealing with modern large-scale circuits, remains unsolved. To resolve this challenge, we propose an absolute shrinkage deep kernel learning, ASDK, which automatically identifies the dominant process variation parameters in a nonlinear-correlated deep kernel and acts as a surrogate model to emulate the expensive SPICE simulation. To further improve the yield estimation efficiency, we propose a novel maximization of approximated entropy reduction for an efficient model update, which is also enhanced with parallel batch sampling for parallel computing, making it ready for practical deployment. Experiments on SRAM column circuits demonstrate the superiority of ASDK over the state-of-the-art (SOTA) approaches in terms of accuracy and efficiency with up to 10.3x speedup over SOTA methods.