FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training
arXiv:2212.03515v16 citationsh-index: 24
Originality Synthesis-oriented
AI Analysis
This addresses the need for efficient signal processing in communication hardware, but it is incremental as it applies existing machine learning methods to a specific domain.
The paper tackled the problem of adapting to time-varying channel impairments in communication systems by implementing an adaptive machine learning equalizer with on-chip training on an FPGA, achieving real-time adaptation capabilities.
We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.