Hardware Acceleration of Lane Detection Algorithm: A GPU Versus FPGA Comparison
This work addresses hardware optimization for lane detection in autonomous vehicles, but it is incremental as it compares existing technologies without introducing new methods.
The paper compares FPGA and GPU implementations of a lane detection algorithm for autonomous driving, focusing on performance metrics like latency and power consumption, but does not provide specific numerical results.
A Complete Computer vision system can be divided into two main categories: detection and classification. The Lane detection algorithm is a part of the computer vision detection category and has been applied in autonomous driving and smart vehicle systems. The lane detection system is responsible for lane marking in a complex road environment. At the same time, lane detection plays a crucial role in the warning system for a car when departs the lane. The implemented lane detection algorithm is mainly divided into two steps: edge detection and line detection. In this paper, we will compare the state-of-the-art implementation performance obtained with both FPGA and GPU to evaluate the trade-off for latency, power consumption, and utilization. Our comparison emphasises the advantages and disadvantages of the two systems.