Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics
This work tackles the problem of hardware scalability and energy efficiency for ML accelerators, which is crucial for advancing AI applications, though it is a conceptual vision rather than an incremental improvement.
The paper addresses the limitations of electronic ML accelerators due to computation density and metallic interconnects by proposing a vision for integrating optical computation and communication into 2.5D chiplet platforms to create sustainable and scalable hardware accelerators.
Domain-specific machine learning (ML) accelerators such as Google's TPU and Apple's Neural Engine now dominate CPUs and GPUs for energy-efficient ML processing. However, the evolution of electronic accelerators is facing fundamental limits due to the limited computation density of monolithic processing chips and the reliance on slow metallic interconnects. In this paper, we present a vision of how optical computation and communication can be integrated into 2.5D chiplet platforms to drive an entirely new class of sustainable and scalable ML hardware accelerators. We describe how cross-layer design and fabrication of optical devices, circuits, and architectures, and hardware/software codesign can help design efficient photonics-based 2.5D chiplet platforms to accelerate emerging ML workloads.