Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity
This work addresses the hardware efficiency problem for implementing reliable AI systems using BNNs, offering a domain-specific solution that is incremental in nature.
The authors tackled the resource-intensive hardware implementation of Bayesian Neural Networks (BNNs) by leveraging the inherent stochasticity of nanoscale memristive devices, specifically Phase Change Memory (PCM), to create a binary spiking network architecture that achieves hardware accuracy and expected calibration error matching an 8-bit fixed-point implementation while projecting over 9× savings in core area transistor count.
Bayesian Neural Networks (BNNs) can overcome the problem of overconfidence that plagues traditional frequentist deep neural networks, and are hence considered to be a key enabler for reliable AI systems. However, conventional hardware realizations of BNNs are resource intensive, requiring the implementation of random number generators for synaptic sampling. Owing to their inherent stochasticity during programming and read operations, nanoscale memristive devices can be directly leveraged for sampling, without the need for additional hardware resources. In this paper, we introduce a novel Phase Change Memory (PCM)-based hardware implementation for BNNs with binary synapses. The proposed architecture consists of separate weight and noise planes, in which PCM cells are configured and operated to represent the nominal values of weights and to generate the required noise for sampling, respectively. Using experimentally observed PCM noise characteristics, for the exemplary Breast Cancer Dataset classification problem, we obtain hardware accuracy and expected calibration error matching that of an 8-bit fixed-point (FxP8) implementation, with projected savings of over 9$\times$ in terms of core area transistor count.