A Bit-Parallel Deterministic Stochastic Multiplier
arXiv:2302.08324v15 citationsh-index: 15
Originality Incremental advance
AI Analysis
This addresses the need for more efficient hardware multipliers in computing systems, representing a strong specific gain rather than a broad paradigm shift.
The paper tackles the problem of inefficient stochastic multipliers by introducing a bit-parallel deterministic design, achieving up to a 10.6×10^4 improvement in area-energy-latency product and a 32.2% reduction in computational error compared to prior methods.
This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6$\times$10$^4$, while improving the computational error by 32.2\%, compared to three prior stochastic multipliers.