Iterative Circuit Repair Against Formal Specifications
This addresses the challenge of automated circuit synthesis and repair for hardware design, representing a domain-specific incremental advance.
The paper tackles the problem of repairing defective sequential circuits against formal specifications in linear-time temporal logic (LTL) using Transformer models, achieving state-of-the-art improvements of 6.8 percentage points on held-out instances and 11.8 percentage points on an out-of-distribution dataset.
We present a deep learning approach for repairing sequential circuits against formal specifications given in linear-time temporal logic (LTL). Given a defective circuit and its formal specification, we train Transformer models to output circuits that satisfy the corresponding specification. We propose a separated hierarchical Transformer for multimodal representation learning of the formal specification and the circuit. We introduce a data generation algorithm that enables generalization to more complex specifications and out-of-distribution datasets. In addition, our proposed repair mechanism significantly improves the automated synthesis of circuits from LTL specifications with Transformers. It improves the state-of-the-art by $6.8$ percentage points on held-out instances and $11.8$ percentage points on an out-of-distribution dataset from the annual reactive synthesis competition.