DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
This addresses the problem of high computational overhead in DNN training and inference for AI applications, offering a novel architecture that improves efficiency without relying on immature technologies.
The paper tackles the computational cost of matrix multiplications in DNNs by proposing DAISM, an in-SRAM digital multiplier-based accelerator that uses conventional memory for bit-parallel computations, achieving up to two orders of magnitude higher area efficiency compared to state-of-the-art counterparts with competitive energy efficiency.
DNNs are widely used but face significant computational costs due to matrix multiplications, especially from data movement between the memory and processing units. One promising approach is therefore Processing-in-Memory as it greatly reduces this overhead. However, most PIM solutions rely either on novel memory technologies that have yet to mature or bit-serial computations that have significant performance overhead and scalability issues. Our work proposes an in-SRAM digital multiplier, that uses a conventional memory to perform bit-parallel computations, leveraging multiple wordlines activation. We then introduce DAISM, an architecture leveraging this multiplier, which achieves up to two orders of magnitude higher area efficiency compared to the SOTA counterparts, with competitive energy efficiency.