Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks
This addresses security vulnerabilities in hardware encryption systems against side-channel attacks, presenting an incremental improvement in protection techniques.
The paper tackles thwarting power side-channel attacks by analyzing an island-based random dynamic voltage scaling (iRDVS) approach, showing that iRDVS with four voltage islands cannot be broken with 200k encryption traces and that a test chip using iRDVS passed security tests while unprotected variants failed.
In this paper, we describe and analyze an island-based random dynamic voltage scaling (iRDVS) approach to thwart power side-channel attacks. We first analyze the impact of the number of independent voltage islands on the resulting signal-to-noise ratio and trace misalignment. As part of our analysis of misalignment, we propose a novel unsupervised machine learning (ML) based attack that is effective on systems with three or fewer independent voltages. Our results show that iRDVS with four voltage islands, however, cannot be broken with 200k encryption traces, suggesting that iRDVS can be effective. We finish the talk by describing an iRDVS test chip in a 12nm FinFet process that incorporates three variants of an AES-256 accelerator, all originating from the same RTL. This included a synchronous core, an asynchronous core with no protection, and a core employing the iRDVS technique using asynchronous logic. Lab measurements from the chips indicated that both unprotected variants failed the test vector leakage assessment (TVLA) security metric test, while the iRDVS was proven secure in a variety of configurations.