Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition
This work addresses memory limitations for FPGA-based CNN accelerators, offering an incremental improvement through a novel compression method.
The paper tackled the problem of deploying CNNs to dataflow accelerators hindered by on-chip memory constraints by proposing Mixed-TD, a framework using layer-specific tensor decomposition, achieving 1.73x to 10.29x throughput per DSP on state-of-the-art CNNs.
Neural Network designs are quite diverse, from VGG-style to ResNet-style, and from Convolutional Neural Networks to Transformers. Towards the design of efficient accelerators, many works have adopted a dataflow-based, inter-layer pipelined architecture, with a customised hardware towards each layer, achieving ultra high throughput and low latency. The deployment of neural networks to such dataflow architecture accelerators is usually hindered by the available on-chip memory as it is desirable to preload the weights of neural networks on-chip to maximise the system performance. To address this, networks are usually compressed before the deployment through methods such as pruning, quantization and tensor decomposition. In this paper, a framework for mapping CNNs onto FPGAs based on a novel tensor decomposition method called Mixed-TD is proposed. The proposed method applies layer-specific Singular Value Decomposition (SVD) and Canonical Polyadic Decomposition (CPD) in a mixed manner, achieving 1.73x to 10.29x throughput per DSP to state-of-the-art CNNs. Our work is open-sourced: https://github.com/Yu-Zhewen/Mixed-TD