Adaptive Planning Search Algorithm for Analog Circuit Verification
This work addresses the need for efficient pre-silicon verification in integrated circuits, which is incremental as it applies existing ML methods to a specific domain problem.
The paper tackles the problem of reducing time for analog circuit verification by proposing a machine learning approach that uses Gaussian process surrogate models to iteratively propose difficult operating condition configurations, resulting in better estimation of circuit responses and identifying a failure for a real circuit.
Integrated circuit verification has gathered considerable interest in recent times. Since these circuits keep growing in complexity year by year, pre-Silicon (pre-SI) verification becomes ever more important, in order to ensure proper functionality. Thus, in order to reduce the time needed for manually verifying ICs, we propose a machine learning (ML) approach, which uses less simulations. This method relies on an initial evaluation set of operating condition configurations (OCCs), in order to train Gaussian process (GP) surrogate models. By using surrogate models, we can propose further, more difficult OCCs. Repeating this procedure for several iterations has shown better GP estimation of the circuit's responses, on both synthetic and real circuits, resulting in a better chance of finding the worst case, or even failures, for certain circuit responses. Thus, we show that the proposed approach is able to provide OCCs closer to the specifications for all circuits and identify a failure (specification violation) for one of the responses of a real circuit.