High-definition event frame generation using SoC FPGA devices
This enables faster event frame generation for vision algorithms like object classification/detection, but is incremental as it focuses on hardware implementation trade-offs.
The paper tackled implementing high-resolution (1280x720) event data accumulation and projection on FPGA devices, confirming feasibility while identifying hardware resource challenges and trade-offs across different data representations and AMD Xilinx platforms.
In this paper we have addressed the implementation of the accumulation and projection of high-resolution event data stream (HD -1280 x 720 pixels) onto the image plane in FPGA devices. The results confirm the feasibility of this approach, but there are a number of challenges, limitations and trade-offs to be considered. The required hardware resources of selected data representations, such as binary frame, event frame, exponentially decaying time surface and event frequency, were compared with those available on several popular platforms from AMD Xilinx. The resulting event frames can be used for typical vision algorithms, such as object classification and detection, using both classical and deep neural network methods.