When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA
This work addresses deployment barriers for BayesNNs in safety-critical applications like medical imaging and autonomous driving, offering an incremental improvement in hardware optimization.
The paper tackles the high algorithmic complexity and poor hardware performance of Bayesian Neural Networks (BayesNNs) by proposing a multi-exit Monte-Carlo Dropout-based BayesNN and an FPGA accelerator framework, achieving higher energy efficiency than CPU, GPU, and other state-of-the-art implementations.
Bayesian Neural Networks (BayesNNs) have demonstrated their capability of providing calibrated prediction for safety-critical applications such as medical imaging and autonomous driving. However, the high algorithmic complexity and the poor hardware performance of BayesNNs hinder their deployment in real-life applications. To bridge this gap, this paper proposes a novel multi-exit Monte-Carlo Dropout (MCD)-based BayesNN that achieves well-calibrated predictions with low algorithmic complexity. To further reduce the barrier to adopting BayesNNs, we propose a transformation framework that can generate FPGA-based accelerators for multi-exit MCD-based BayesNNs. Several novel optimization techniques are introduced to improve hardware performance. Our experiments demonstrate that our auto-generated accelerator achieves higher energy efficiency than CPU, GPU, and other state-of-the-art hardware implementations.