SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR
This addresses the problem of inefficient hardware generation from HLS for designers, offering a novel automated approach that can outperform manual optimizations.
The paper tackles the performance gap between hardware designs from high-level synthesis (HLS) tools and manual implementations by proposing SEER, a super-optimization tool that automatically rewrites software programs into efficient HLS code, achieving up to 38x performance improvement within 1.4x area overhead.
High-level synthesis (HLS) is a process that automatically translates a software program in a high-level language into a low-level hardware description. However, the hardware designs produced by HLS tools still suffer from a significant performance gap compared to manual implementations. This is because the input HLS programs must still be written using hardware design principles. Existing techniques either leave the program source unchanged or perform a fixed sequence of source transformation passes, potentially missing opportunities to find the optimal design. We propose a super-optimization approach for HLS that automatically rewrites an arbitrary software program into efficient HLS code that can be used to generate an optimized hardware design. We developed a toolflow named SEER, based on the e-graph data structure, to efficiently explore equivalent implementations of a program at scale. SEER provides an extensible framework, orchestrating existing software compiler passes and hardware synthesis optimizers. Our work is the first attempt to exploit e-graph rewriting for large software compiler frameworks, such as MLIR. Across a set of open-source benchmarks, we show that SEER achieves up to 38x the performance within 1.4x the area of the original program. Via an Intel-provided case study, SEER demonstrates the potential to outperform manually optimized designs produced by hardware experts.