VerilogEval: Evaluating Large Language Models for Verilog Code Generation
This work addresses the need for standardized evaluation in hardware design automation, but it is incremental as it adapts existing methods to a new domain.
The paper tackles the problem of evaluating large language models for Verilog code generation by proposing a benchmarking framework with a dataset of 156 problems from HDLBits, and shows that supervised fine-tuning with synthetic data improves model performance.
The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specifically for evaluating LLM performance in the context of Verilog code generation for hardware design and verification. We present a comprehensive evaluation dataset consisting of 156 problems from the Verilog instructional website HDLBits. The evaluation set consists of a diverse set of Verilog code generation tasks, ranging from simple combinational circuits to complex finite state machines. The Verilog code completions can be automatically tested for functional correctness by comparing the transient simulation outputs of the generated design with a golden solution. We also demonstrate that the Verilog code generation capability of pretrained language models could be improved with supervised fine-tuning by bootstrapping with LLM generated synthetic problem-code pairs.