3SAT on an All-to-All-Connected CMOS Ising Solver Chip
For researchers using Ising hardware for combinatorial optimization, this work provides practical methods to map NP-complete problems onto existing chips.
The paper solves 3SAT on a CMOS Ising chip with all-to-all connectivity, demonstrating that without their decomposition and mapping strategies, the hardware cannot solve SATLIB benchmarks.
This work solves 3SAT, a classical NP-complete problem, on a CMOS-based Ising hardware chip with all-to-all connectivity. The paper addresses practical issues in going from algorithms to hardware. It considers several degrees of freedom in mapping the 3SAT problem to the chip - using multiple Ising formulations for 3SAT; exploring multiple strategies for decomposing large problems into subproblems that can be accommodated on the Ising chip; and executing a sequence of these subproblems on CMOS hardware to obtain the solution to the larger problem. These are evaluated within a software framework, and the results are used to identify the most promising formulations and decomposition techniques. These best approaches are then mapped to the all-to-all hardware, and the performance of 3SAT is evaluated on the chip. Experimental data shows that the deployed decomposition and mapping strategies impact SAT solution quality: without our methods, the CMOS hardware cannot achieve 3SAT solutions on SATLIB benchmarks.