Domain Knowledge Graph Construction Via A Simple Checker
This work addresses knowledge graph construction for semiconductor chip design companies, focusing on confidentiality and scalability, but appears incremental as it adapts existing methods to a specific domain.
The paper tackles the problem of constructing knowledge graphs from hardware-design domain texts, proposing an oracle-checker scheme using GPT-3.5, and demonstrates its practicality with the RISC-V ISA specification as an example.
With the availability of large language models, there is a growing interest for semiconductor chip design companies to leverage the technologies. For those companies, deployment of a new methodology must include two important considerations: confidentiality and scalability. In this context, this work tackles the problem of knowledge graph construction from hardware-design domain texts. We propose an oracle-checker scheme to leverage the power of GPT3.5 and demonstrate that the essence of the problem is in distillation of domain expert's background knowledge. Using RISC-V unprivileged ISA specification as an example, we explain key ideas and discuss practicality of our proposed oracle-checker approach.