Advancing The Rate-Distortion-Computation Frontier For Neural Image Compression
This addresses the efficiency bottleneck for neural image compression on consumer hardware, though it is incremental in improving existing methods.
The paper tackled the challenge of making neural image compression models more efficient for widespread deployment by studying the rate-distortion-computation (RDC) frontier, resulting in a novel architecture that achieves state-of-the-art rate savings of 23.1% over BPG without significantly increasing computational costs.
The rate-distortion performance of neural image compression models has exceeded the state-of-the-art for non-learned codecs, but neural codecs are still far from widespread deployment and adoption. The largest obstacle is having efficient models that are feasible on a wide variety of consumer hardware. Comparative research and evaluation is difficult due to the lack of standard benchmarking platforms and due to variations in hardware architectures and test environments. Through our rate-distortion-computation (RDC) study we demonstrate that neither floating-point operations (FLOPs) nor runtime are sufficient on their own to accurately rank neural compression methods. We also explore the RDC frontier, which leads to a family of model architectures with the best empirical trade-off between computational requirements and RD performance. Finally, we identify a novel neural compression architecture that yields state-of-the-art RD performance with rate savings of 23.1% over BPG (7.0% over VTM and 3.0% over ELIC) without requiring significantly more FLOPs than other learning-based codecs.