NECLETLGDec 14, 2023

Language Modeling on a SpiNNaker 2 Neuromorphic Chip

arXiv:2312.09084v315 citationsh-index: 12AICAS
Originality Incremental advance
AI Analysis

This work addresses energy efficiency for AI inference tasks, particularly in resource-constrained environments, though it is incremental as it builds on existing event-based methods.

The authors tackled the problem of high energy consumption in large language models by implementing the first language model on a neuromorphic chip (SpiNNaker 2) using an event-based architecture (EGRU), achieving performance matching LSTMs and demonstrating significant energy efficiency gains for single-batch inference.

As large language models continue to scale in size rapidly, so too does the computational power required to run them. Event-based networks on neuromorphic devices offer a potential way to reduce energy consumption for inference significantly. However, to date, most event-based networks that can run on neuromorphic hardware, including spiking neural networks (SNNs), have not achieved task performance even on par with LSTM models for language modeling. As a result, language modeling on neuromorphic devices has seemed a distant prospect. In this work, we demonstrate the first-ever implementation of a language model on a neuromorphic device - specifically the SpiNNaker 2 chip - based on a recently published event-based architecture called the EGRU. SpiNNaker 2 is a many-core neuromorphic chip designed for large-scale asynchronous processing, while the EGRU is architected to leverage such hardware efficiently while maintaining competitive task performance. This implementation marks the first time a neuromorphic language model matches LSTMs, setting the stage for taking task performance to the level of large language models. We also demonstrate results on a gesture recognition task based on inputs from a DVS camera. Overall, our results showcase the feasibility of this neuro-inspired neural network in hardware, highlighting significant gains versus conventional hardware in energy efficiency for the common use case of single batch inference.

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