RLPlanner: Reinforcement Learning based Floorplanning for Chiplets with Fast Thermal Analysis
This addresses thermal and performance optimization in chiplet floorplanning, an incremental advance in electronic design automation.
The paper tackled the problem of floorplanning for chiplet-based systems by introducing RLPlanner, which uses reinforcement learning and a fast thermal evaluation method to minimize wirelength and temperature, achieving a 20.28% average improvement in the objective and over 120x speed-up in thermal analysis.
Chiplet-based systems have gained significant attention in recent years due to their low cost and competitive performance. As the complexity and compactness of a chiplet-based system increase, careful consideration must be given to microbump assignments, interconnect delays, and thermal limitations during the floorplanning stage. This paper introduces RLPlanner, an efficient early-stage floorplanning tool for chiplet-based systems with a novel fast thermal evaluation method. RLPlanner employs advanced reinforcement learning to jointly minimize total wirelength and temperature. To alleviate the time-consuming thermal calculations, RLPlanner incorporates the developed fast thermal evaluation method to expedite the iterations and optimizations. Comprehensive experiments demonstrate that our proposed fast thermal evaluation method achieves a mean absolute error (MAE) of 0.25 K and delivers over 120x speed-up compared to the open-source thermal solver HotSpot. When integrated with our fast thermal evaluation method, RLPlanner achieves an average improvement of 20.28\% in minimizing the target objective (a combination of wirelength and temperature), within a similar running time, compared to the classic simulated annealing method with HotSpot.