Optimal Synthesis of Finite State Machines with Universal Gates using Evolutionary Algorithm
This work addresses circuit design efficiency for hardware engineers, but it is incremental as it applies an existing evolutionary method to a specific benchmark set.
The paper tackled the problem of optimizing finite state machine synthesis to reduce on-chip area and circuit cost, achieving an average 30% reduction in total gates using Cartesian Genetic Programming on MCNC91 benchmark circuits.
This work presents an optimization method for the synthesis of finite state machines. The focus is on the reduction in the on-chip area and the cost of the circuit. A list of finite state machines from MCNC91 benchmark circuits have been evolved using Cartesian Genetic Programming. On the average, almost 30% of reduction in the total number of gates has been achieved. The effects of some parameters on the evolutionary process have also been discussed in the paper.