Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
This work addresses a bottleneck in hardware design automation for FPGA developers, offering a significant but incremental improvement over existing GNN methods.
The paper tackles the slow turnaround time in high-level synthesis (HLS) for FPGA design by proposing a hierarchical GNN-based method to predict post-route quality of results (QoR) from C/C++ programs, achieving less than 10% prediction error and reducing design space exploration runtime to tens of minutes with an average ADRS of 6.91%.
High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route quality of results (QoR) are considered during optimization. To tackle this issue, we propose a hierarchical post-route QoR prediction approach for FPGA HLS, which features: (1) a modeling flow that directly estimates latency and post-route resource usage from C/C++ programs; (2) a graph construction method that effectively represents the control and data flow graph of source code and effects of HLS pragmas; and (3) a hierarchical GNN training and prediction method capable of capturing the impact of loop hierarchies. Experimental results show that our method presents a prediction error of less than 10% for different types of QoR metrics, which gains tremendous improvement compared with the state-of-the-art GNN methods. By adopting our proposed methodology, the runtime for design space exploration in HLS is shortened to tens of minutes and the achieved ADRS is reduced to 6.91% on average.