MicroNAS: Zero-Shot Neural Architecture Search for MCUs
This work addresses the challenge of efficient NAS for edge computing on MCUs, offering a practical solution with significant speed-ups, though it is incremental as it builds on existing NAS methods.
The paper tackles the problem of resource-intensive Neural Architecture Search (NAS) for microcontroller units (MCUs) by proposing MicroNAS, a hardware-aware zero-shot framework that achieves up to 1104x improvement in search efficiency and discovers models with over 3.23x faster MCU inference while maintaining similar accuracy.
Neural Architecture Search (NAS) effectively discovers new Convolutional Neural Network (CNN) architectures, particularly for accuracy optimization. However, prior approaches often require resource-intensive training on super networks or extensive architecture evaluations, limiting practical applications. To address these challenges, we propose MicroNAS, a hardware-aware zero-shot NAS framework designed for microcontroller units (MCUs) in edge computing. MicroNAS considers target hardware optimality during the search, utilizing specialized performance indicators to identify optimal neural architectures without high computational costs. Compared to previous works, MicroNAS achieves up to 1104x improvement in search efficiency and discovers models with over 3.23x faster MCU inference while maintaining similar accuracy